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LTC3552-1 1 35521fa standalone linear li-ion battery charger and dual synchronous buck converter the ltc ? 3552-1 is a complete constant-current/constant- voltage linear charger and dual ? xed output dc/dc con- verter for single cell lithium-ion batteries. its dfn package and low external component count make the LTC3552-1 ideally suited for portable applications. furthermore, the LTC3552-1 is designed to work within usb power speci? cations. no external sense resistor or external blocking diode are required due to the internal mosfet architecture. the charge voltage is ? xed at 4.2v and the charge current is programmed with a resistor. the charge cycle terminates when the charge current drops below the programmed termination threshold after the ? nal ? oat voltage is reached. when the input supply (wall adapter or usb supply) is removed, the LTC3552-1 enters a low current state dropping the battery drain current to less than 2a. thermal regulation maximizes charge rate without risk of overheating. the synchronous step-down switching regulators generate ? xed output voltages of 1.8v and 1.575v. the switching frequency is set at 2.25mhz, allowing the use of small surface mount inductors and capacitors. cellular telephones, pdas, mp3 players bluetooth applications programmable charge current up to 950ma complete linear charger and dual dc/dc regulator dual fixed outputs: 1.8v at 800ma 1.575v at 400ma no mosfet, sense resistor or blocking diode required thermal regulation maximizes charge rate without risk of overheating* charges directly from a usb port programmable charge current termination preset 4.2v charge voltage with 1% accuracy charge current monitor output for gas gauging* automatic recharge charge status output power present output soft-start limits inrush current low quiescent current buck converter (40a) current mode operation, constant frequency (2.25mhz) low pro? le (5mm 3mm 0.75mm) dfn package applicatio s u features descriptio u typical applicatio u single cell li-ion battery charger with c/5 termination and dual dc/dc converter v in 4.5v to 6.5v v out2 1.575v/ 400ma v out1 1.8v/ 800ma 35521 ta01 LTC3552-1 v in gnd c out2 10 f cer c out1 10 f cer iterm prog sw2 v out2 run1 run2 bat v cc sw1 v out1 800ma v fb2 v fb1 c ff2 330pf c ff1 330pf 4.7 h 1 f 10 f 2.2 h chrg pwr en 619 ? 1.24k + 4.2v 1-cell li-ion battery load current (ma) 1 80 efficiency (%) power loss (mw) 90 100 10 100 1000 35521 tao1b 70 75 85 95 65 60 10 100 1000 1 0.1 channel 1 channel 2 v out2 = 1.575v v out1 = 1.8v v in = 3.6v burst mode operation ef? ciency curve/ power loss of regulators , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6522118, 6700364, 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
LTC3552-1 2 35521fa input supply voltage (v in ) ......................... C0.3v to 10v prog, iterm .................................. C0.3v to v in + 0.3v bat .............................................................. C0.3v to 7v chrg , pwr , en ....................................... C0.3v to 10v bat short-circuit duration ............................ continuous bat pin current ..........................................................1a prog pin current ....................................................1ma v cc supply voltage ...................................... C0.3v to 6v v out1 , v out2 , run1, run2 voltages .............................C0.3v to v cc +0.3v v fb1 , v fb2 ........................................C0.3v to v cc + 0.3v sw1, sw2 voltage ...........................C0.3v to v cc + 0.3v ambient operating temperature range (note 2) .................................... C40c to 85c maximum junction temperature (note 8) ............ 125c storage temperature range ................... C65c to 125c (note 1) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 5v, v cc = 3.6v unless otherwise noted. symbol parameter conditions min typ max units battery charger v in input supply voltage 4.25 8 v i in input supply current charge mode (note 4) standby mode shutdown mode r prog = 10k charge terminated en = 5v, v in < v bat or v in < v uv 0.4 200 25 1 500 50 ma a a v float regulated output (float) voltage 0c t a 85c, 4.3v < v in < 8v 4.158 4.2 4.242 a i bat bat pin current r prog = 10k, current mode r prog = 2k, current mode standby mode, v bat = 4.2v shutdown mode (en = 5v, v in < v bat or v in < v uv ) sleep mode, v in = 0v 92 465 100 500 C2.5 1 1 105 535 C6 2 2 ma ma a a a v uv v in undervoltage lockout voltage from v in low to high 3.7 3.8 3.92 v v uvhys v in undervoltage lockout hysteresis 150 200 300 mv v en (il) en pin input low voltage 0.4 0.7 v v en (ih) en pin input high voltage 0.7 1 v r en en pin pull-down resistor 1.2 2 5 ? v asd v in C v bat lockout threshold voltage v in from low to high v in from high to low 70 5 100 30 140 50 mv mv i term charge termination current threshold r term = 1k r term = 5k 90 17.5 100 20 110 22.5 ma ma electrical characteristics absolute axi u rati gs w ww u package/order i for atio uu w 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 en pwr v in prog sw1 v cc v out1 v fb1 iterm bat chrg run2 sw2 run1 v out2 v fb2 top view dhc package 16-lead (5mm 3mm) plastic dfn t jmax = 125c, ja = 40c/w (note 3) exposed pad is ground (pin 17) must be soldered to pcb order part number dhc part marking ltc3552edhc-1 35521 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges.
LTC3552-1 3 35521fa symbol parameter conditions min typ max units v prog prog pin voltage r prog = 10k, current mode 0.93 1 1.07 v v chrg chrg pin output low voltage i chrg = 5ma 0.35 0.6 v v pwr pwr pin output low voltage i pwr = 5ma 0.35 0.6 v v rechrg recharge battery threshold voltage v float C v rechrg , 0c < t a < 85c 60 100 140 mv t lim junction temperature in constant- temperature mode 120 c r on-chrg chargers power fet on resistance (between v in and bat) 600 m t ss-chrg charger soft-start time i bat = 0 to i bat = 1000v/r prog 100 s t rechrg recharge comparator filter time v bat high to low 0.75 2 4.5 ms t term termination comparator filter time i bat drops below charge termination threshold 0.4 1 2.5 ms switching regulator v cc operating voltage range for converter 2.5 5.5 v v out1 output voltage feedback of regulator 1 0c t a 85c (note 5) C40c t a 85c (note 5) 1.764 1.755 1.8 1.8 1.836 1.836 v v v out2 output voltage feedback of regulator 2 0c t a 85c (note 5) C40c t a 85c (note 5) 1.544 1.536 1.575 1.575 1.607 1.607 v v v line_reg reference voltage line regulation v cc = 2.5v to 5.5v (note 5) 0.3 0.5 %/v v load_reg output voltage load regulation (note 5) 0.5 % i s input dc supply current (note 6) active mode sleep mode shutdown v out1 = 1.5v, v out2 = 1.3v v out1 = 1.89v, v out2 = 1.65v run = 0v, v cc = 5.5v 700 40 0.1 950 60 1 a a a f osc oscillator frequency v out1 = 1.8v, v out2 = 1.575v 1.8 2.25 2.7 mhz i lim peak switch current limit regulator 1 peak switch current limit regulator 2 v cc = 3v, duty cycle < 35% v cc = 3v, duty cycle < 35% 0.95 0.6 1.2 0.7 1.6 0.9 a a r ds(on) converter top switch on-resistance converter bottom switch on-resistance (note 7) (note 7) 0.35 0.3 0.45 0.45 i sw(lkg) switch leakage current v cc = 5v, v run = 0v, v fb = 0v 0.01 1 a v run run threshold voltage 0.3 1 1.5 v i run run leakage current 0.01 1 a the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 5v, v cc = 3.6v unless otherwise noted. electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3552e-1 is guaranteed to meet performance speci? cations from 0c to 85c speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: failure to solder the exposed backside of the package to the pc board will result in a thermal resistance much higher than 40c/w. see thermal considerations. note 4 : supply current includes prog pin current and iterm pin current (approximately 100a each) but does not include any current delivered to the battery through the bat pin (approximately 100ma). note 5: the converter is tested in a proprietary test mode that connects the output of the error ampli? er to the sw pin, which is connected to an external servo loop. note 6: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 7: the regulator power switch on-resistances are guaranteed by correlation to wafer level measurements. note 8: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja )
LTC3552-1 4 35521fa v prog (v) 0 0 i bat (ma) 100 200 300 400 600 0.2 0.4 0.6 0.8 35521 g03 1 1.2 500 v in = 5v r prog = 2k r term = 2k temperature ( c) ?50 v prog (v) 0.9975 1.0000 1.0025 25 75 35521 g02 0.9950 0.9925 0.9900 ?25 0 50 1.0050 1.0075 1.0100 100 v in = 5v v bat = v bsense = 4v r prog = 10k v in (v) 4 0.985 v prog (v) 0.990 0.995 1.000 1.005 1.015 4.5 5 5.5 6 35521 g01 6.5 7 7.5 8 1.010 v bat = 4v r prog = 10k v bat (v) 2.4 i bat (ma) 400 500 600 3.3 3.9 35521 g09 300 200 2.7 3 3.6 4.2 4.5 100 0 v in = 5v ja = 40 c/w r prog = 2k charge current vs battery voltage prog pin voltage vs supply voltage (constant-current mode) prog pin voltage vs temperature charge current vs prog pin voltage typical perfor a ce characteristics uw t a = 25 c unless otherwise speci? ed. battery charger v chrg (v) 0 i chrg (ma) 20 25 30 35 35521 g07 15 10 12 467 5 0 t a = ?40 c t a = 25 c t a = 90 c v in = 5v v bat = 4v v pwr (v) 0 i pwr (ma) 20 25 30 35 35521 g08 15 10 12 467 5 0 t a = ?40 c t a = 25 c t a = 90 c v in = 5v v bat = 4v chrg pin i-v curve (pull-down state) pwr pin i-v curve (pull-down state) temperature ( c) ?50 4.185 v float (v) 4.190 4.195 4.200 4.205 4.215 ?25 02550 35521 g05 75 100 4.210 v in = 5v r prog = 10k i bat (ma) 0 v float (v) 4.24 300 35521 g04 4.18 4.14 100 200 400 4.12 4.10 4.26 4.22 4.20 4.16 500 600 700 v in = 5v r prog = 1.25k v in (v) 4.185 v float (v) 4.190 4.195 4.200 4.205 4.215 35521 g06 4.210 4 4.5 5 5.5 6 6.5 7 7.5 8 r prog = 10k regulated output (float) voltage vs charge current regulated output (float) voltage vs temperature regulated output (float) voltage vs supply voltage
LTC3552-1 5 35521fa v in (v) 0 i bat (ma) 100 200 300 400 600 35521 g10 500 4 4.5 5 5.5 6 6.5 7 7.5 8 r prog = 2k r prog = 10k v bat = 4v ja = 40 c/w temperature ( c) ?50 i bat (ma) 400 500 600 25 75 35521 g11 300 200 ?25 0 50 100 125 100 0 v in = 5v v bat = 4v ja = 40 c/w r prog = 2k onset of thermal regulation r prog = 10k temperature ( c) ?50 350 r ds(on) (m ? ) 400 450 500 600 550 650 700 ?25 02550 35521 g12 75 125 100 v in = 4.2v i bat = 100ma r prog = 2k temperature ( c) ?50 4.04 v rechrg (v) 4.06 4.08 4.10 4.12 4.16 ?25 02550 35521 g13 75 100 4.14 v in = 5v r prog = 10k charge current vs supply voltage charge current vs ambient temperature power fet on resistance vs temperature recharge threshold voltage vs temperature typical perfor a ce characteristics uw battery charger t a = 25 c unless otherwise speci? ed.
LTC3552-1 6 35521fa typical perfor a ce characteristics uw 35521 g16 v cc = 3.6v v out2 = 1.575v i load = 40ma to 400ma regulator 2; circuit of figure 2 v out2 200mv/div i l 200ma/div i load 40ma- 400ma 200ma/div 20 s/div v cc (v) 35521 g17 100 95 90 85 80 75 70 65 60 23455.56 2.5 3.5 4.5 efficiency (%) v out1 = 1.8v, regulator 1 burst mode operation circuit of figure 2 i out = 1ma i out = 10ma i out = 100ma i out = 800ma 2.5 2.4 2.3 2.2 2.1 2.0 frequency (mhz) temperature ( c) ?50 25 75 35521 g18 ?25 0 50 100 125 v cc = 3.6v 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 frequency deviation (%) v cc (v) 2 35521 g19 3 456 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 output voltage error (%) temperature ( c) ?50 25 75 35521 g20 ?25 0 50 100 125 v cc = 3.6v v cc (v) 1 500 450 400 350 300 250 200 46 35521 g21 2 3 57 r ds(on) (m ? ) main switch synchronous switch junction temperature ( c) ?50 550 500 450 400 350 300 250 200 150 100 25 75 35521 g22 ?25 0 50 100 150 125 r ds(on) (m ? ) main switch synchronous switch v cc = 3.6v v cc = 4.2v v cc = 2.7v switching regulator ef? ciency vs supply voltage oscillator frequency vs temperature oscillator frequency error vs supply voltage output voltage error vs temperature r ds(on) vs supply voltage r ds(on) vs junction temperature burst mode operation load step load step t a = 25 c unless otherwise speci? ed. 35521 g15 v cc = 3.6v v out1 = 1.8v i load = 80ma to 800ma regulator 1; circuit of figure 2 v out1 200mv/div i load : 80ma- 800ma 500ma/div i l 500ma/div 20 s/div 35521 g14 v cc = 3.6v v out1 = 1.8v i load = 60ma regulator 1; circuit of figure 2 sw 5v/div v out1 ripple 20mv/div i l 200ma/div 2 s/div
LTC3552-1 7 35521fa ef? ciency vs load current load regulation typical perfor a ce characteristics uw load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 35521 g26 v out1 = 1.8v regulator 1; circuit of figure 2 v cc = 2.7v v cc = 3.6v v cc = 4.2v load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 35521 g27 v out2 = 1.575v regulator 2; circuit of figure 2 v cc = 2.7v v cc = 3.6v v cc = 4.2v switching regulator t a = 25 c unless otherwise speci? ed. ef? ciency vs load current load regulation load current (ma) 1 efficiency (%) 100 95 90 85 80 75 70 65 60 10 100 1000 35521 g23 v cc = 3.6v burst mode operation circuit of figure 2 v out1 = 1.8v v out2 = 1.575v load current (ma) 1 v out error (%) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 10 100 1000 35521 g24 v cc = 3.6v burst mode operation circuit of figure 2 v out1 = 1.8v v out2 = 1.575v line regulation v cc (v) 2.5 v out error (%) 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 4.5 35521 g25 3.5 5.5 3 5 4 i out = 200ma v out1 = 1.8v v out2 = 1.575v
LTC3552-1 8 35521fa pi fu ctio s uuu iterm (pin 1): charge termination program. the charge termination current threshold is programmed by connect- ing a 1% resistor, r term , to ground. the current threshold iterm, is set by the following formula: i v r r v i term term term term == 100 100 , bat (pin 2): charge current output. provides charge cur- rent to the battery from the internal p-channel mosfet, and regulates the ? nal ? oat voltage to 4.2v. an internal precision resistor divider from this pin sets the ? oat volt- age. this divider is disconnected in shutdown mode to minimize current drain from the battery. chrg (pin 3): charge status open-drain output. when the battery is charging, the chrg pin is pulled low by an internal n-channel mosfet. when the charge cycle is completed, chrg becomes high impedance. run2 (pin 4): regulator 2 enable. forcing this pin to v cc enables regulator 2, while forcing it to gnd causes regulator 2 to shut down. this pin must be driven; do not ? oat. sw2 (pin 5): regulator 2 switch node connection to the inductor. this pin swings from v cc to gnd. run1 (pin 6): regulator 1 enable. forcing this pin to v cc enables regulator 1, while forcing it to gnd causes regulator 1 to shut down. this pin must be driven; do not ? oat. v out2 (pin 7): output voltage feedback pin for regula- tor 2. internal resistors divide the output voltage down for comparison to the internal reference voltage. v fb2 (pin 8): output feedback for regulator 2. receives the feedback voltage from internal resistive divider across the output. normal voltage for this pin is 0.6v. v fb1 (pin 9): output feedback for regulator 1. receives the feedback voltage from internal resistive divider across the output. normal voltage for this pin is 0.6v. v out1 (pin 10): output voltage feedback pin for regula- tor 1. internal resistors divide the output voltage down for comparison to the internal reference voltage. v cc (pin 11): buck regulators input supply. provides power to the switchers. must be closely decoupled to gnd. sw1 (pin 12): regulator 1 switch node connection to the inductor. this pin swings from v cc to gnd. prog (pin 13): charge current program and charge current monitor. charge current is programmed by con- necting a 1% resistor, r prog , to ground. when charging in constant-current mode, this pin servos to 1v. in all modes, the voltage on this pin can be used to measure the charge current using the following formula: i v r bat prog prog = 1000 this pin is clamped to approximately 2.4v. driving this pin to voltages beyond the clamp voltage should be avoided. v in (pin 14): charger input supply. provides power to the charger. v in can range from 4.25v to 8v. this pin should be bypassed with at least a 1f capacitor. when v in is within 100mv of the bat pin voltage, the charger enters shutdown mode dropping the battery drain current to less than 2a. pwr (pin 15): power supply status open-drain out- put. when v in is greater than the undervoltage lock- out threshold and at least 100mv above v bat , the pwr pin is pulled to ground; otherwise, the pin is high impedance. en (pin 16): enable input. a logic high on the en pin will put the charger into shutdown mode where the battery drain current is reduced to less than 2a and the supply current is reduced to less than 50a. a logic low or ? oating the en pin (allowing an internal 2m pull-down resistor to pull this pin low) enables charging. exposed pad (gnd) (pin 17): ground. the exposed backside of the package (pin 17) is ground and must be soldered to the pcb for maximum heat transfer.
LTC3552-1 9 35521fa ? + ? + ? + ? + ea uvdet ovdet 0.6v 0.65v 0.55v ? + 0.35v uv ov i th switching logic and blanking circuit s r q q rs latch burst ? + i comp i rcmp anti shoot- thru burst clamp slope comp en sleep 0.6v ref osc osc regulator 2 (identical to regulator 1) r1 = 240k, r2 = 120k, for regulator 1 r1 = 195k, r2 = 120k, for regulator 2 shutdown v cc v cc regulator 1 sw1 sw2 5 ? ? + ? + ? + ? + 120 c t die t a ma ca c1 1 1 1000 va r1 bat r2 r3 1v 0.1v r4 r5 iterm 5 a r ter m ref 1.21v v in chrg en gnd term pwr charge shdn en logic pwr prog r prog 16 15 10 6 4 7 run1 run2 v out2 8 v fb2 v out1 9 v fb1 3 11 12 5 1 13 17 14 2 r1 r2 r enable v fb v cc v cc block diagra w
LTC3552-1 10 35521fa operatio u the LTC3552-1 is made up of two circuit blocks: a stand- alone constant-current/constant-voltage linear charger for a single-cell lithium-ion battery and a high ef? ciency dual dc/dc switching regulator. the charger can deliver up to 950ma of charge current (using a good thermal pcb lay- out) with a ? nal ? oat voltage accuracy of 1%. an internal p-channel power mosfet and thermal regulation circuitry are included. no blocking diode or external current sense resistor is required; furthermore, the charger is capable of operating from a usb power source. the switching regulators use a constant frequency, cur- rent mode step-down architecture. both main (p-chan- nel mosfet) and synchronous (n-channel mosfet) switches are internal. the LTC3552-1 requires no exter- nal diodes or sense resistors. lithium-ion battery charger normal charge cycle a charge cycle begins when the voltage at the v in pin rises above the uvlo threshold level and a 1% program resistor is connected from the prog pin to ground. the charger enters constant-current mode where the pro- grammed charge current is supplied to the battery. when the bat pin approaches the ? nal ? oat voltage (4.2v), the charger enters constant-voltage mode and the charge cur- rent begins to decrease. when the charge current drops to the programmed termination threshold (set by the external resistor r term ), the charge cycle ends. figure 1 shows the state diagram of a typical charge cycle. charge status indicator ( chrg ) the open drain charge status output has two states: pull- down and high impedance. the pull-down state indicates that the charger is in a charge cycle. once the charge cycle has terminated or the charger is disabled, the pin becomes high impedance. automatic recharge once the charge cycle terminates, the charger continuously monitors the voltage on the bat pin using a comparator with a 2ms ? lter time (t recharge ). a charge cycle restarts when the battery voltage falls below 4.10v (which corre- figure 1. state diagram of a typical charge cycle sponds to approximately 80% to 90% battery capacity). this ensures that the battery is kept at, or near, a fully charged condition and eliminates the need for periodic charge cycle initiations. the chrg output enters a pull- down state during recharge cycles. if the battery is removed from the charger, a sawtooth waveform of approximately 100mv appears at the charger output. this is caused by the repeated cycling between termination and recharge events. this cycling results in pulsing at the chrg output; an led connected to this pin will exhibit a pulsing pattern, indicating to the user that a battery is not present. the frequency of the sawtooth is dependent on the amount of output capacitance. power supply status indicator ( pwr ) the power supply status output has two states: pull-down and high impedance. the pull-down state indicates that v in is above the uvlo threshold (3.8v) and is also 100mv above the battery voltage. if these conditions are not met, the pwr pin is high impedance indicating that the charger is unable to charge the battery. charge current soft-start the charger includes a soft-start circuit to minimize the inrush current at the start of a charge cycle. when a charge cycle is initiated, the charge current ramps from zero to full-scale current over a period of approximately 100s. this has the effect of minimizing the transient current load on the power supply during start-up. charge mode full current chrg: strong pull-down shutdown mode chrg: hi-z en driven low or uvlo condition ends en driven high or uvlo condition i cc drops to <25 a power on i term < 100mv standby mode no charge current chrg: hi-z 2.9v < bat < 4.1v 35521 f01
LTC3552-1 11 35521fa operatio u thermal limiting an internal thermal feedback loop reduces the pro- grammed charge current if the die temperature attempts to rise above a preset value of approximately 120c. this feature protects the charger from excessive temperature and allows the user to push the limits of the power handling capability of a given circuit board without risk of damag- ing the charger. the charge current can be set according to typical (not worst case) ambient temperature with the assurance that the charger will automatically reduce the current in worst-case conditions. dfn package power considerations are discussed further in the applications information section. undervoltage lockout (uvlo) an internal undervoltage lockout circuit monitors the in- put voltage and keeps the charger in shutdown mode until v in rises above the undervoltage lockout threshold. the uvlo circuit has a built-in hysteresis of 200mv. also, to protect against reverse current in the power mosfet, the uvlo circuit keeps the charger in shutdown mode if v in falls to within 30mv of the bat voltage. if the uvlo comparator is tripped, the charger will not come out of shutdown mode until v in rises 100mv above the bat voltage. manual shutdown at any point in the charge cycle, the charger can be put into shutdown mode by driving the en pin high. this reduces the battery drain current to less than 2a and the v in supply current to less than 50a. when in shutdown mode, the chrg pin is in the high impedance state. a new charge cycle can be initiated by driving the en pin low. an internal resistor pull-down on this pin forces the charger to be enabled if the pin is allowed to ? oat. dual switching regulator the regulators use a current mode architecture with a constant operating frequency of 2.25mhz. both regulators share the same clock and run in-phase. the output voltages are ? xed at 1.8v for regulator 1 and at 1.575v for regulator 2. the resistive divider feedback networks are integrated inside the LTC3552-1. an error ampli? er compares the divided output voltage (v fb ) with a reference voltage of 0.6v and adjusts the peak inductor current accordingly. main regulator control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle when the v out feedback voltage is below the reference voltage. the current ? ows into the inductor and the load in- creases until the current limit is reached. the switch turns off and energy stored in the inductor ? ows through the bottom switch (n-channel mosfet) into the load until the next clock cycle. the peak inductor current is controlled by the internally compensated i th voltage, which is the output of the error ampli? er. this ampli? er compares the v fb to the 0.6v reference (see block diagram). when the load current increases, the v fb voltage decreases slightly below the reference. this decrease causes the error ampli- ? er to increase the i th voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the run pin to ground. low load current operation when the load is relatively light, the regulator automati- cally switches into burst mode operation, where the pmos switch operates intermittently based on load demand with a ? xed peak inductor current. by running cycles periodi- cally, the switching losses which are dominated by the gate charge losses of the power mosfets are minimized. the main control loop is interrupted when the output voltage reaches the desired regulated value. a voltage comparator trips when i th is below 0.35v, shutting off the switch and reducing the power. the output capacitor and the induc- tor supply the power to the load until i th exceeds 0.65v, turning on the switch and the main control loop which starts another cycle. dropout operation when the v cc input supply voltage decreases approach- ing the output voltage, the duty cycle increases to 100% which is the dropout condition. in dropout, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. an important design consideration is that the r ds(on) of
LTC3552-1 12 35521fa operatio u the p-channel switch increases with decreasing input supply voltage (see typical performance characteristics). therefore, the user should calculate the power dissipa- tion when the regulator is used at 100% duty cycle with low input voltage (see thermal considerations in the applications information section). low supply voltage operation to prevent unstable operation, the regulator incorporates an undervoltage lockout circuit which shuts down the regulators when the v cc voltage drops below approxi- mately 1.65v. applicatio s i for atio wu u u a typical LTC3552-1 application circuit is shown in figure 2. external component selection is driven by the charging requirements and the switching regulators load requirements. programming charge current the charge current is programmed using a single resistor from the prog pin to ground. the charge current out of the bat pin is 1000 times the current out of the prog pin. the program resistor and the charge current are calculated using the following equations: r v i i v r prog chg chg prog == 1000 1000 , charge current out of the bat pin can be determined anytime by monitoring the prog pin voltage and using the following equation: i v r bat prog prog = 1000 programming charge termination the charge cycle terminates when the charge current falls below the programmed termination threshold. this thresh- old is set by connecting an external resistor, r term , from the iterm pin to ground. the charge termination current figure 2. LTC3552-1 basic circuit * any external sources that hold the iterm pin above 100mv will prevent the LTC3552-1 from terminating a charge cycle. ** these equations apply only when the iterm pin is shorted to the prog pin. threshold (i term ) is set by the following equation: i v r ir r r term term chg prog term term == = 100 10 100 , vv i term the termination condition is detected by using an internal ? ltered comparator to monitor the iterm pin. when the iterm pin voltage drops below 100mv* for longer than t term (typically 1ms), charging is terminated. the charge current is latched off and the charger enters standby mode where the input supply current drops to 200a. (note: termination is disabled in thermal limiting mode). i term can be set to be one tenth of i chg by shorting the iterm pin to the prog pin, thus eliminating the need for external resistor r term . when con? gured in this way, i term is always set to i chg /10, and the programmed charge current is set by the equation: i v r r v i chg prog prog chg == 500 500 , ** when charging, transient loads on the bat pin can cause the iterm pin to fall below 100mv for short periods of time before the dc charge current has dropped to 10% of the programmed value. the 1ms ? lter time (t term ) on the termination comparator ensures that transient loads of this nature do not result in premature charge cycle termi- nation. once the average charge current drops below the programmed termination threshold, the charger terminates the charge cycle and ceases to provide any current out of the bat pin. in this state, any load on the bat pin must be supplied by the battery. v in 4.5v to 6.5v v out2 1.575v/ 400ma v out1 1.8v/ 800ma 35521 f02 LTC3552-1 v in gnd c out2 10 f cer c out1 10 f cer iterm prog sw2 v out2 run1 run2 bat v cc sw1 v out1 600ma v fb2 v fb1 c ff2 330pf c ff1 330pf 4.7 h 1 f 10 f 2.2 h chrg pwr en 825 ? 1.65k + 4.2v 1-cell li-ion battery
LTC3552-1 13 35521fa with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs size requirements and any radiated ? eld/emi requirements than on what the LTC3552-1 requires to operate. table 1 shows some typical surface mount inductors that work well in LTC3552-1 applications. table 1. representative surface mount inductors part number value (h) dcr ( max) max dc current (a) size w l h (mm) sumida cdrh3d16 2.2 3.3 4.7 0.075 0.110 0.162 1.20 1.10 0.90 3.8 3.8 1.8 sumida cdrh2d11 1.5 2.2 0.068 0.170 0.900 0.780 3.2 3.2 1.2 sumida cmd4d11 2.2 3.3 0.116 0.174 0.950 0.770 4.4 5.8 1.2 murata lqh32cn 1.0 2.2 0.060 0.097 1.00 0.79 2.5 3.2 2.0 toko d312f 2.2 3.3 0.060 0.260 1.08 0.92 2.5 3.2 2.0 murata elt5kt 3.3 4.7 0.17 0.20 1.00 0.95 4.5 5.4 1.2 input capacitor (c in ) selection in continuous mode, the input current of the converter is a square wave with a duty cycle of approximately v out /v cc . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: ii vvv v rms max out cc out cc ? () where the maximum average output current i max equals the peak current minus half the peak-to-peak ripple cur- rent, i max = i lim C i l /2.this formula has a maximum at v cc = 2v out , where i rms = i out /2. this simple worst-case is commonly used to design because even signi? cant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours life-time. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1f to 1f ceramic capacitor is also recommended on v cc for high frequency decoupling, when not using an all ceramic capacitor solution. the charger constantly monitors the bat pin voltage in standby mode. if this voltage drops below the 4.1v re- charge threshold (v rechrg ), another charge cycle begins and charge current is once again supplied to the battery. to manually restart a charge cycle when in standby mode, the input voltage must be removed and reapplied, or the charger must be shut down and restarted using the en pin. switching regulator inductor selection the inductor value has a direct effect on inductor ripple current i l , which decreases with higher inductance and increases with higher v cc or v out : ?= ? ? ? ? ? ? ? i v fl v v l out o out cc 1 accepting larger values of i l allows the use of low inductances, but results in higher output ripple voltage, greater core losses, and lower output current capability. a reasonable starting point for setting ripple current is i l = 0.3 ? i out(max) , where i out(max) is 800ma for regulator 1 and 400ma for regulator 2. the largest ripple current i l occurs at the maximum input voltage. to guarantee that the ripple cur- rent stays below a speci? ed maximum, the inductor value should be chosen according to the following equation: l v fi v v out ol out cc max =? ? ? ? ? ? ? () ? 1 the inductor value will also have an effect on burst mode operation. the transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher rip-ple current which causes this to occur at lower load cur-rents. this causes a dip in ef? ciency in the upper range of low current operation. in burst mode operation, lower induc- tance values will cause the burst frequency to increase. inductor core selection different core materials and shapes will change the size/current and price/current relationship of an induc- tor. toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors applicatio s i for atio wu u u
LTC3552-1 14 35521fa applicatio s i for atio wu u u output capacitor (c out ) selection the selection of c out is driven by the required esr to minimize ripple voltage and load step transients. typically, once the esr requirement is satis? ed, the capacitance is adequate for ? ltering. the output ripple ( v out ) is determined by ?? + ? ? ? ? ? ? viesr fc out l o out 1 8 where f o = operating frequency, c out = output capacitance and i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. with i l = 0.3 ? i out(max) the output ripple will be less than 100mv at maximum v cc and f o = 2.25mhz with esr cout < 150m . once the esr requirements for c out have been met, the rms current rating generally far exceeds the i ripple(p-p) requirement, except for an all ceramic solution. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms cur- rent handling requirement of the application. aluminum electrolytic, special polymer, ceramic and solid tantalum capacitors are all available in surface mount packages. the oscon semiconductor dielectric capacitor avail- able from sanyo has the lowest esr (size) product of any aluminum electrolytic at a somewhat higher price. special polymer capacitors, such as sanyo poscap, panasonic special polymer (sp), and kemet a700, of- fer very low esr, but have a lower capacitance density than other types. tantalum capacitors have the highest capacitance density, but they have a higher esr and it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors have a signi? cantly higher esr, and are often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have the lowest esr and cost, but also have the lowest capacitance density, a high voltage and temperature coef? cient, and exhibit audible piezoelectric effects. in addition, the high q of ceramic capacitors along with trace inductance can lead to signi? cant ringing. in most cases, 0.1f to 1f of x5r dielectric ceramic capacitors should also be placed close to the LTC3552-1 in parallel with the main capacitors for high frequency decoupling. ceramic input and output capacitors higher value, lower cost ceramic capacitors are now be- coming available in smaller case sizes. these are tempting for switching regulator use because of their very low esr. unfortunately, the esr is so low that it can cause loop stability problems. solid tantalum capacitor esr generates a loop zero at 5khz to 50khz that is instrumental in giving acceptable loop phase margin. ceramic capacitors remain capacitive to beyond 300khz and usually resonate with their esl before esr becomes effective. also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating temperature range. to minimize their high temperature and voltage coef? cients, only x5r or x7r ceramic capacitors should be used. a good selection of ceramic capacitors is available from taiyo yuden, avx, kemet, tdk, and murata. great care must be taken when using only ceramic input and output capacitors. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v cc pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is very low, the input and output capacitor must instead ful? ll a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation and the output capacitor size. typically, 3-4 cycles are required to respond to a load step, but only in the ? rst cycle does the output drop linearly. the output droop, v droop , is usually about 2-3 times the linear drop of the ? rst cycle. thus, a good place to start is with the output capacitor size of approximately: c i fv out out o droop ? ? ? ? ? ? 25 . ? more capacitance may be required depending on the duty cycle and load step requirements. in most applications,
LTC3552-1 15 35521fa applicatio s i for atio wu u u the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 10f ceramic capacitor is usually enough for these conditions. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or dis- charge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a feedforward capacitor, c ff , is added externally to improve the high frequency response. capacitor c ff provides phase lead by creating a high frequency zero with r1, which improves the phase margin. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. in some applications, a more severe transient can be caused by switching loads with large (>1f) input capacitors. the discharged load input capacitors are effectively put in par- allel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap ? controller is designed speci? cally for this purpose and usually incorporates cur- rent limiting, short-circuit protection, and soft-start. ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: % ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3552-1 circuits: 1) v cc quiescent current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1) the v cc current is the dc supply current given in the electrical characteristics which excludes mosfet dri- ver and control currents. v cc current results in a small (<0.1%) loss that increases with v cc , even at no load. 2) the switching current is the sum of the mosfet driver and control currents. the mosfet driver current re- sults from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from v cc to ground. the resulting dq/dt is a current out of v cc that is typically much larger than the dc bias current. in continuous mode, i gatechg = f o (q t + q b ), where q t and q b are the gate charges of the internal top and bottom mosfet switches. the gate charge losses are proportional to v cc and thus their effects will be more pronounced at higher supply voltages. 3) i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current ? ows through inductor l, but is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (d) as follows: r sw = (r ds(on)top )(d) + (r ds(on)bot )(1 C d) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 4) other hidden losses such as copper trace and internal battery resistances can account for additional ef? ciency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate hot swap is a trademark of linear technology corporation.
LTC3552-1 16 35521fa applicatio s i for atio wu u u charge storage and very low esr at the switching fre- quency. other losses include diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. thermal considerations the battery chargers thermal regulation feature and the switching regulators high ef? ciency make it unlikely that the LTC3552-1 will dissipate enough power to exceed its maximum junction temperature. however, in applica- tions where the LTC3552-1 is running at high ambient temperature with low supply voltage and high duty cycles, the power dissipated may result in excessive junction temperatures. to prevent the LTC3552-1 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated will raise the junction temperature above the maximum rating. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated and ja is the ther- mal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as an example, consider the case when the battery char- ger is idle, and both regulators are operating at an input voltage of 2.7v with a load current of 400ma and 800ma and an ambient temperature of 70c. from the typical performance characteristics graph of switch resistance, the r ds(on) resistance of the main switch is 0.425 . therefore, power dissipated by each regulator is: p d = i 2 ? r ds(on) = 272mw and 68mw the dhc16 package junction-to-ambient thermal resis- tance, ja , is 40c/w. therefore, the junction temperature of the regulator operating in a 70c ambient temperature is approximately: t j = (0.272 + 0.068) ? 40 + 70 = 83.6c which is below the absolute maximum junction tempera- ture of 125c. the majority of the LTC3552-1 power dissipation comes from the battery charger. fortunately, the LTC3552-1 au- tomatically reduces the charge current during high power conditions using a patented thermal regulation circuit. thus, it is not necessary to design for worst-case power dissipa- tion scenarios. the conditions that cause the LTC3552-1 to reduce charge current through thermal feedback can be approximated by considering the power dissipated in the ic. the approximate ambient temperature at which the thermal feedback begins to protect the ic is: t a = 120c C p d ja t a = 120c C (p d(charger) + p d(regulator) ) ? ja most of the chargers power dissipation is generated from the internal charger mosfet. thus, the power dissipation is calculated to be: p d(charger) = (v in C v bat ) ? i bat v in is the charger supply voltage, v bat is the battery volt- age and i bat is the charge current. example: an LTC3552-1 operating from a 5v supply is programmed to supply 800ma full-scale current to a discharged li-ion battery with a voltage of 3.3v. for simplicity, assume the regulators are disabled and dis- sipate no power. the charger power dissipation is calculated to be: p d(charger) = (5v C 3.3v) ? 800ma = 1.36w thus, the ambient temperature at which the LTC3552-1 charger begins to reduce the charge current is approxi- mately: t a = 120c C 1.36w ? 40c/w t a = 120c C 54.4c t a = 65.6c the LTC3552-1 can be used above 65c ambient but the charge current will be reduced from the programmed 800ma. the approximate current at a given ambient temperature can be approximated by: i ct vv bat a in bat ja = 120 ? (? ) using the previous example with an ambient temperature of 70c (and no heat dissipation from the regulator), the charge current will be reduced to approximately:
LTC3552-1 17 35521fa applicatio s i for atio wu u u i cc vv cw c ca i bat = = 120 70 533 40 50 68 ? (?.) / / b bat ma = 735 the previous analysis can be repeated to take into account the power dissipation of the regulator by: i ct t vv bat a rise regulator in bat j = ? 120 ? (? () ) aa however, the regulator typically dissipates signi? cantly less heat than the charger (even in worst-case situations), the calculations here should work well as an approximation. moreover, when thermal feedback reduces the charge current, the voltage at the prog pin is also reduced pro- portionally. it is important to remember that LTC3552-1 applications do not need to be designed for worst-case thermal conditions since the ic will automatically reduce charge current when the junction temperature reaches approximately 120c. in order to deliver maximum charge current under all conditions, it is critical that the exposed metal pad on the backside of the LTC3552-1 package is soldered to the pc board ground. failure to make thermal contact between the exposed pad on the backside of the package and the copper board will result in thermal resistances far greater than 40c/w. as an example, a correctly soldered LTC3552-1 can deliver over 800ma to a battery from a 5v supply at room temperature. without a good backside thermal connection, this number will drop considerably. battery charger stability considerations the constant-voltage mode feedback loop is stable with-out an output capacitor, provided a battery is connected to the charger output. with no battery present, an output capacitor on the bat pin is recommended to reduce ripple voltage. when using high value, low esr ceramic capacitors, it is recommended to add a 1 resistor in series with the capacitor. no series resistor is needed if tantalum capaci- tors are used. in constant-current mode, the prog pin is in the feedback loop, not the battery. the constant-current mode stability is affected by the impedance at the prog pin. with no additional capacitance on the prog pin, the charger is stable with program resistor values as high as 20k; however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin is loaded with a capacitance, c prog , the following equation can be used to calculate the maximum resistance value for r prog : r c prog prog 1 210 5 average, rather than instantaneous charge current may be of interest to the user. for example, when the switch- ing regulators operating in burst mode ? are connected in parallel with the battery, the average current being pulled out of the bat pin is typically of more interest than the instantaneous current pulses. in such a case, a simple rc ? lter can be used on the prog pin to measure the average battery current, as shown in figure 3. a 10k resistor has been added between the prog pin and the ? lter capacitor to ensure stability. figure 3. isolating capacitive load on prog pin and filtering LTC3552-1 gnd prog r prog 10k c filter 35521 f03 charge current monitor circuitry v in bypass capacitor many types of capacitors can be used for input bypassing; however, caution must be exercised when using multilayer ceramic capacitors. because of the self-resonant and high q characteristics of some types of ceramic capacitors, high voltage transients can be generated under some start-up conditions such as connecting the charger input to a live power source. adding a 1.5 resistor in series with an x5r ceramic capacitor will minimize start-up voltage transients. for more information, see application note 88. reverse polarity input voltage protection in some applications, protection from reverse polarity voltage on v in is desired. if the supply voltage is high enough, a series blocking diode can be used. in burst mode is a registered trademark of linear technology corporation.
LTC3552-1 18 35521fa applicatio s i for atio wu u u design example as a design example, assume the LTC3552-1 is used in a single lithium-ion battery-powered cellular phone ap- plication. starting with the charger, choosing r prog to be 1.24k programs the charger for 806ma. a good rule of thumb for i terminate is one tenth the full charge current, so r iterm is picked to be 1.24k (i terminate = 80ma). for the switching regulators powered from the battery, v cc can range from 4.2v to about 2.7v. the load requires a maximum of 800ma in active mode and 2ma in standby mode. regulator 1 output voltage is 1.8v. since the load still needs power in standby, burst mode operation is used for good low load ef? ciency. first, calculate the inductor value for about 30% ripple current at maximum v cc : l v mhz ma v v h =? ? ? ? ? ? ? = 18 2 25 240 1 18 42 19 . . . . . choosing a vendors closest inductor value of 2.2h, results in a maximum ripple current of: ? i v mhz h v v ma l = ? ? ? ? ? ? ? = 18 225 22 1 18 42 208 . .. . . for cost reasons, a ceramic capacitor will be used. c out selection is then based on load step droop instead of esr requirements. for a 5% output droop: c ma mhz v f out = () = 25 800 225 5 25 71 . .%. . a good standard value is 10f. since the impedance of a li-ion battery is very low, c in is typically 10f. following the same procedure, for v out2 = 1.575v, inductor value can be derived as 4.7h, and output capacitor is 4.7f. figure 2 shows the complete schematic for this design example. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3552-1. these items are also illustrated graphically in the layout diagram of figure 5. check the following in your layout: 1. does the capacitor c in connect to the power v cc and gnd (exposed pad) as closely as possible? this ca- pacitor provides the ac current to the internal power mosfets and their drivers. 2. the feedback signals v out should be routed away from noisy components and traces, such as the sw line, and its trace should be minimized. 3. are the c out and l1 closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . 4. keep sensitive components away from the sw pins. the input capacitor c in should be routed away from the sw traces and the inductors. 5. a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the gnd pin at one point and should not share the high current path of c in or c out . 6. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. these copper areas should be connected to v cc or gnd. figure 5. layout diagram figure 4. low loss input reverse polarity protection 3552-1 f05 l1 l2 bold lines indicate high current paths LTC3552-1 gnd v in sw2 v out2 v fb2 v cc sw1 v out1 v fb1 v out2 v out1 c in c s c out1 c out2 c ff2 c ff1 LTC3552-1 v in v in 35521 f04 drain-bulk diode of fet other cases, where the voltage drop must be kept low, a p-channel mosfet can be used (as shown in figure 4).
LTC3552-1 19 35521fa *ogpsnbujpo gvsojtife cz -jofbs 5fdiopmphz $psqpsbujpo jt cfmjf wfe up cf bddvsbuf boe sfmjbcmf )pxfwfs opsftqpotjcjmjuzjtbttvnfegpsjutvtf-jofbs5fdio pmphz$psqpsbujponblftopsfqsftfoub ujpouibuuifjoufsdpoofdujpopgjutdjsdvjutbteftdsjcfeifsf joxjmmopujogsjohfpofyjtujohqbufousjhiut applicatio s i for atio wu u u figure 6. suggested layout full-featured single-cell li-ion charger plus step-down converter dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706) v out2 v out1 v in l2 gnd c s 35521 f06 via to v out1 c out2 16 15 14 13 12 11 10 9 gnd 17 1 2 3 4 5 6 7 8 en pwr v in prog sw1 v cc v out1 v fb1 iterm bat chrg run2 sw2 run1 v out2 v fb2 c ff1 c ff2 l1 c out1 gnd v in 5v v out2 1.575v/ 400ma v out1 1.8v/800ma 35521 ta02 LTC3552-1 v in gnd c out2 10 f cer c out1 10 f cer iterm prog sw2 v out2 run2 bat v cc run1 sw1 v out1 500ma v fb2 v fb1 c ff2 330pf c ff1 330pf 4.7 h 1 f 10 f 2.2 h chrg pwr en + 4.2v 1-cell li-ion battery 2k 1k 1k 1k typical applicatio u package descriptio u 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05
LTC3552-1 20 35521fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt/lwi 0606 rev a ? printed in usa part number description comments ltc3455 dual dc/dc converter with usb power management and li-ion battery charger ef? ciency >96%, accurate usb current limiting (500ma/100ma), 4mm 4mm qfn-24 package ltc3548 dual synchronous, 400ma/800ma, 2.25hmz step-down dc/dc regulator high ef? ciency: up to 95%, i q : 40 a, 2.25mhz frequency, msop-10 and 3mm 3mm dfn-10 packages ltc3550-1 dual input usb/ac adapter li-ion battery charger with 600ma synchronous buck converter buck ef? ciency: 93%, charger: automatic input power detection and selection, charge current: 950ma, usb compatible, 3mm 5mm dfn-16 package ltc4053-4.2 usb compatible li-ion battery charger with thermal regulation charges single-cell li-ion batteries, from usb, ms package ltc4054/ltc4054x standalone linear li-ion battery charger with integrated pass transistor in thinsot tm thermal regulation prevents overheating, c/10 termination, c/10 indicator, up to 800ma charge current ltc4055 usb power controller and battery charger charges single-cell li-ion batteries directly from usb port, thermal regulation, 4mm 4mm qfn-16 package ltc4058/ltc4058x standalone 950ma lithium-ion charger in dfn c/10 charge termination, battery kelvin sensing, 7% charge accuracy ltc4061 standalone linear li-ion battery charger with thermistor input charge current programmable up to 1a ltc4066 standalone linear li-ion battery charger with thermistor input charges single-cell li-ion from usb port, dfn package ltc4068/ltc4068x standalone linear li-ion battery charger with programmable termination charge current up to 950ma, thermal regulation, 3mm 3mm dfn-8 package ltc4412 low-loss powerpath tm controller in thinsot v in : 3v to 28v, automatic switching between dc sources related parts typical applicatio u li-ion charger and step-down converters with powerpath ? powerpath and thinsot are registered trademarks of linear technology corporation. v in 5v v out2 1.575v/ 400ma v out1 1.8v/800ma 35521 ta03 LTC3552-1 v in gnd c out2 10 f cer c out1 10 f cer iterm prog sw2 v out2 v cc run2 run1 sw1 v out1 800ma v fb2 v fb1 c ff2 330pf c ff1 330pf 4.7 h 1 f 4.7 f 2.2 h chrg pwr en bat + 4.2v 1-cell li-ion battery 1.24k 1k 1k 1k 1k

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